upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 200
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 5
200
Figure 5-3
acknowledgement
5.2.1 Operation
CPU processing
If a non-maskable interrupt is generated, the CPU performs the following
processing, and transfers control to the handler routine:
(1)
(2)
(3)
(4)
(5)
The processing configuration of a non-maskable interrupt is shown in
Figure 5-3.
Processing configuration of non-maskable interrupt
Preliminary User’s Manual U17566EE1V2UM00
INTC
Saves the restored PC to FEPC.
Saves the current PSW to FEPSW.
Writes exception code 0010H to the higher halfword (FECC) of ECR.
Sets the NP and ID bits of the PSW and clears the EP bit.
Sets the handler address corresponding to the non-maskable interrupt to
the PC, and transfers control.
FEPC
FEPSW
ECR.FECC ← Exception
PSW.NP
PSW.EP
PSW.ID
PC
Non-maskable interrupt
Interrupt service
NMI input
PSW.NP
request
←
← PSW
← 1
← 0
← 1
← NMI-Handler
0
code
address
Restored PC
1
Interrupt request pending
Interrupt Controller (INTC)
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