upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 208

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 5
208
Interrupt request o
Interrupt request s
Interrupt request i
Interrupt request l
Figure 5-8
(level 2)
(level 2)
(level 3)
(level 1)
Main routine
EI
Interrupt request n
2.
Example of processing in which another interrupt request is issued
while an interrupt is being processed (2/2)
Preliminary User’s Manual U17566EE1V2UM00
request p
Interrupt request u
Interrupt
(level 2)
Interrupt request k
The default priority in the figure indicates the relative priority between two
interrupt requests.
Interrupt
request j
(level 3)
(level 3)
(level 1)
(level 1)
request m
(level 2)
(level 2)
request t
Interrupt
Interrupt
EI
Processing of o
EI
request q
Interrupt
(level 1)
Processing of j
Processing of s
Processing of i
Processing of l
Processing of n
Note 1
Processing of u
Note 2
Processing of t
Processing of m
EI
Processing of p
request r
Interrupt
(level 0)
Processing of k
EI
Processing of q
Pending interrupt requests t and u are
acknowledged after processing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
If levels 3 to 0 are acknowledged
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt requests m and n are held pending
because processing of l is performed in the
interrupt disabled status.
Pending interrupt requests are acknowledged after
processing of interrupt request l.
At this time, interrupt requests n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Processing of r
Interrupt Controller (INTC)