upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 586

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
586
Condition for clearing (STCFn = 0)
• Cleared by IICCn.STTn = 1
• After reset
Condition for clearing (IICBSYn = 0)
• When stop condition is detected
• After reset
Condition for clearing (STCENn = 0)
• When start condition is detected
• After reset
STCENn
IICBSYn
STCFn
0
1
0
1
0
1
Initial Value
Address
Start condition issued
Start condition cannot be issued, STTn bit cleared
Bus released status
Bus communication status
Start conditions cannot be generated until a stop condition is detected following operation enable
(IICEn bit = 1).
Start conditions can be generated even if a stop condition is not detected following operation
enable (IICEn = 1).
Access
(3)
IICFn - IICn flag registers
The registers set the I
This register can be read/written in 8-bit or 1-bit units.
STCFn and IICBSYn bits are read-only.
<base> + A
00
IICRSVn enables/disables the communication reservation function.
The initial value of the IICBSYn bit is set by using the STCENn bit (see
“Cautions“ on page 624).
The IICRSVn and STCENn bits can be written only when operation of I
disabled (IICCn.IICEn = 0). After operation is enabled, IICFn can be read.
Preliminary User’s Manual U17566EE1V2UM00
STCFn
H
. This register is cleared by any reset.
R
7
IICBSYn
H
R
6
Initial start enable trigger
2
R/W
Cn operation mode and indicate the I
5
0
I
2
Cn bus status
STTn clear
Condition for setting (STCFn = 1)
•
Condition for setting (IICBSYn = 1)
• When start condition is detected
• By setting the IICCn.IICEn bit when the STCENn =
Condition for setting (STCENn = 1)
• Setting by instruction
is cleared during communication reservation is
disabled (IICRSVn = 1).
0
When start condition is not issued and STTn flag
R/W
4
0
R/W
3
0
R/W
2
0
STCENn IICRSVn
2
C bus status.
R/W
1
I
2
C Bus (IIC)
2
R/W
Cn is
0