upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 158

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 4
158
Bit position
1 to 0
6
3
Table 4-18
Bit name
PSM[1:0]
OSCDIS
CMODE
PSM register contents
Preliminary User’s Manual U17566EE1V2UM00
Function
Watch Calibration Timer clock selection:
Main oscillator disable/enable control during and after power save mode:
Caution:
OSCDIS determines also the behaviour of the main oscillator during and after
power save mode. The effect of this bit differs, depending on the power save mode.
• Sub-WATCH mode
During Sub-WATCH mode the main oscillator is always stopped. OSCDIS
determines whether the main oscillator shall be started and chosen as CPU clock
source or should remain stopped after Sub-WATCH mode release.
• WATCH mode
This bit determines whether the main oscillator shall be stopped or remain in
operation during WATCH mode. In either case after WATCH mode release the CPU
is operating on the main oscillator.
Power save mode selection:
It is not possible to switch to IDLE or WATCH mode when the CPU is operated by a
sub clock. If IDLE or WATCH mode is selected during sub clock operation, the Sub-
WATCH mode will be entered.
0: PCLK1.
1: Main oscillator.
0: Main oscillator enabled.
1: Main oscillator disabled.
0: Main oscillator enable.
1: Main oscillator disable.
0: Main oscillator enable.
1: Main oscillator disable.
The main oscillator is started after Sub-WATCH mode release and the CPU is
supplied with the main oscillator clock, after the oscillation stabilization time has
elapsed.
The main oscillator remains stopped after Sub-WATCH release.
The CPU is supplied with the selected sub clock—either sub oscillator or ring
oscillator (see bit PCC.SOSCP).
Since the reset value of OSCDIS is 1 and PCC.SOSCP is 0 the CPU starts
always with the ring oscillator clock after reset release.
In both cases, the application software must start the main oscillator by clearing
the OSCDIS bit. After the oscillator stabilization time has elapsed (see bit
CGSTAT.OSCSTAT), the main oscillator can be used as system clock source by
setting the PCC register accordingly.
The main oscillator is operating during WATCH mode.
After WATCH mode release the CPU is supplied with the main oscillator clock.
The main oscillator is stopped during WATCH mode.
After WATCH mode release the main oscillator is started and the CPU is
supplied with the main oscillator clock, after the oscillation stabilization time has
elapsed.
PSM1
0
0
1
1
If OSCDIS is set to 1, the main oscillator clock supply for the Watch
Timer and the LCD Controller/Driver are stopped immediately.
Thus these function stop their operation immediately as well, when the
main oscillator is used as the clock source.
PSM0
0
1
0
1
Power save mode
IDLE
STOP
WATCH
Sub-WATCH mode (main oscillator shut down)
Clock Generator