upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 538

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 16
538
transfer rate
transfer rate
transfer rate
Figure 16-12
Maximum
allowable
allowable
Minimum
UARTn
Latch timing
Allowable baud rate range during reception
As shown in Figure 16-12, the receive data latch timing is determined by the
counter set using the UAnCTL2 register following start bit detection. The
transmit data can be normally received if up to the last data (stop bit) can be
received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
FL = (Brate)
Minimum allowable transfer rate:
Therefore, the maximum baud rate that can be received by the destination is
as follows.
Similarly, obtaining the following maximum allowable transfer rate yields the
following.
Preliminary User’s Manual U17566EE1V2UM00
Start bit
Start bit
Start bit
Brate: UARTAn baud rate
k:
FL:
Latch timing margin: 2 clocks
FL min
BRmax
10
----- -
11
FLmax
×
FLmax
-1
Setting value of UAnCTL2.UAnBRS[7:0]
1-bit data length
=
Bit 0
=
=
Bit 0
11 FL
FL
Bit 0
21k 2
------------------ -
(
FLmin 11
20k
×
=
–
11
–
Bit 1
×
×
⁄
Bit 1
k 2
----------- -
FL 11
FL
2k
Bit 1
–
)
×
–
–
1
1 data frame (11 × FL)
×
k
------------
2k
FL
=
+
FLmin
2
-------------------
21k
=
×
22k
FL
FLmax
21k
------------------ -
+
Asynchronous Serial Interface (UARTA)
2
2k
=
Bit 7
×
+
Bit 7
Brate
21k 2
------------------ -
2
×
2k
Bit 7
FL
–
Parity bit
×
Parity bit
FL
Parity bit
Stop bit
Stop bit
Stop bit