upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 207
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Interrupt Controller (INTC)
Interrupt request a
Interrupt request e
Interrupt request g
Interrupt request c
(level 3)
(level 3)
(level 2)
(level 1)
Figure 5-7
Caution
Main routine
Note
EI
Interrupt request f
Interrupt request d
Example of processing in which another interrupt request is issued
while an interrupt is being processed (1/2)
The values of the EIPC and EIPSW registers must be saved before executing
multiple interrupts. When returning from multiple interrupt servicing, restore the
values of EIPC and EIPSW after executing the DI instruction.
1.
Preliminary User’s Manual U17566EE1V2UM00
Interrupt request h
Interrupt
request b
(level 2)
(level 1)
(level 3)
(level 2)
<a> to <u> in the figure are the temporary names of interrupt requests
shown for the sake of explanation.
EI
EI
EI
Processing of a
Processing of c
Processing of d
Processing of e
Processing of f
Processing of g
Processing of h
Processing of b
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.
Chapter 5
207
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