upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 599

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
C Bus (IIC)
Transfer lines
Master (Tx)
Figure 18-11
Slave (Rx)
18.6.6 Wait signal (WAIT)
ACKEn
SDAn
SCLn
SCLn
SCLn
IICn
IICn
(1)
The wait signal (WAIT) is used to notify the communication partner that a
device (master or slave) is preparing to transmit or receive data (i.e., is in a
wait state).
Setting the SCLn pin to low level notifies the communication partner of the wait
status. When the wait status has been cancelled for both the master and slave
devices, the next data transfer can begin.
When master device has a nine-clock wait and slave device has an eight-
clock wait (master: transmission, slave: reception, and IICCn.ACKEn
bit = 1)
Wait signal (1/2)
Preliminary User’s Manual U17566EE1V2UM00
H
D2
6
6
D1
7
7
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock.
D0
8
8
Wait signal
from slave
9
ACK
9
FFH is written to IICn register or
IICCn.WRELn bit is set to 1.
Wait after output
of ninth clock.
Wait signal
from master
IICn data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
Chapter 18
599