upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 395
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
- Current page: 395 of 930
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16-bit Timer/Event Counter P (TMP)
Figure 11-22
CCR0 buffer register
CCR1 buffer register
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
NTTPnCC0 signal
TOPn0 pin output
TOPn1 pin output
16-bit counter
TPnCE bit
FFFFH
0000H
Basic timing in PWM output mode
When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to
0000H, starts counting, and outputs a PWM waveform from the TOPn1 pin.
The active level width, cycle, and duty factor of the PWM waveform can be
calculated as follows.
The PWM waveform can be changed by rewriting the TPnCCRm register while
the counter is operating. The newly written value is reflected when the count
value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
The compare match interrupt request signal INTTPnCC0 is generated when
the 16-bit counter counts next time after its count value matches the value of
the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTPnCC1 is generated when the
count value of the 16-bit counter matches the value of the CCR1 buffer
register.
The value set to the TPnCCRm register is transferred to the CCRm buffer
register when the count value of the 16-bit counter matches the value of the
CCRm buffer register and the 16-bit counter is cleared to 0000H.
Preliminary User’s Manual U17566EE1V2UM00
Active level width = (Set value of TPnCCR1 register) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
Active period
D
(D
10
D
10
00
)
(D
D
D
Cycle
00
10
D
00
D
D
10
10
D
+ 1)
00
00
D
Inactive period
(D
10
D
00
00
− D
10
+ 1)
D
D
11
01
D
01
D
D
D
D
11
11
01
11
D
01
Chapter 11
395
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