upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 523

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Asynchronous Serial Interface (UARTA)
INTUAnT
interrupt
Figure 16-4
Setting of UAnSTT bit
16.5.3 SBF transmission
16.5.4 SBF reception
When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the
transmission enabled status is entered, and SBF transmission is started by
setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit).
Thereafter, a low level the width of bits 13 to 20 specified by the
UAnOPT0.UAnSBL2 to UAnOPT0.UAnSBL0 bits is output. A transmission
enable interrupt request signal (INTUAnT) is generated upon SBF
transmission start. Following the end of SBF transmission, the UAnSTT bit is
automatically cleared. Thereafter, the UART transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to the
UAnTX register, or until the SBF transmission trigger (UAnSTT bit) is set.
SBF transmission
The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit
to 1 and then setting the UAnCTL0.UAnRX bit to 1.
The SBF reception wait status is set by setting the SBF reception trigger
(UAnOPT0.UAnSTR bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status,
the RXDAn pin is monitored and start bit detection is performed.
Following detection of the start bit, reception is started and the internal counter
counts up according to the set baud rate.
When a stop bit is received, if the SBF width is 11 or more bits, normal
processing is judged and a reception complete interrupt request signal
(INTUAnR) is output. The UAnOPT0.UAnSRF bit is automatically cleared and
SBF reception ends. Error detection for the UAnSTR.UAnOVE,
UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed and UART
communication error detection processing is not performed. Moreover, data
transfer of the UARTAn reception shift register and UAnRX register is not
performed and FFH, the initial value, is held. If the SBF width is 10 or fewer
bits, reception is terminated as error processing without outputting an interrupt,
and the SBF reception mode is returned to. The UAnSRF bit is not cleared at
this time.
Preliminary User’s Manual U17566EE1V2UM00
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Stop
bit
Chapter 16
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