upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 328

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 8
328
DMA Transfer
Request CH3
Figure 8-5
8.12.1 Single transfer mode
CPU
8.12 Transfer Mode
Note
CPU
DMA3 CPU DMA3
In single transfer mode, the DMAC releases the bus after each byte/halfword/
word transfer. If there is a subsequent DMA transfer request, transfer is
performed again once. This operation continues until a terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer
request is issued, the higher priority DMA request always takes precedence.
However, if a lower priority DMA transfer request is generated within one clock
after the end of a single transfer, even if the previous higher priority DMA
transfer request signal stays active, this request is not prioritized and the next
DMA transfer after the bus is released for the CPU is a transfer based on the
newly generated, lower priority DMA transfer request.
Figure 8-5 shows a DMAC transfer in single transfer mode. In this example the
DMA channel 3 is used for a single transfer.
Single transfer example 1
The bus is always released
Preliminary User’s Manual U17566EE1V2UM00
Note
Note
CPU
DMA3
Note
CPU
CPU
CPU
CPU
CPU
CPU
DMA3
Note
CPU DMA3 CPU
DMA Controller (DMAC)
DMA chan nel 3 terminal count
CPU
CPU