upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 581

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
Cautions concerning set timing
For master reception:
For master transmission: A start condition cannot be generated normally during the ACK period. Set during the
For slave:
Condition for clearing (STTn = 0)
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• When the LRELn = 1 (communication save)
• When the IICEn= 0 (operation stop)
• After reset
C Bus (IIC)
device
STTn
0
1
Start condition is not generated.
When bus is released (in STOP mode):
A start condition is generated (for starting as master). The SDAn line is changed from high level to
low level and then the start condition is generated. Next, after the rated amount of time has
elapsed, the SCLn line is changed to low level.
During communication with a third party:
If the communication reservation function is enabled (IICFn.IICRSVn = 0)
• This trigger functions as a start condition reserve flag. When set, it releases the bus and then
If the communication reservation function is disabled (IICRSVn = 1)
• The IICFn.STCFn bit is set. This trigger does not generate a start condition.
In the wait state (when master device):
automatically generates a start condition.
A restart condition is generated after the wait is released.
Note
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
Cannot be set during transfer. Can be set only when the ACKEn bit has been set to 0
and the slave has been notified of final reception.
wait period.
Even when the communication reservation function is disabled
(IICRSVn bit = 1), the communication reservation status is entered.
Clearing the IICEn bit to 0 invalidates the signals of this flag.
The STTn bit is 0 if it is read immediately after data setting.
Note
Start condition trigger
Condition for setting (STTn = 1)
• Set by instruction
Chapter 18
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