upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 274
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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DWC0
DWC1
Chapter 7
274
Bit position
15
15
0
0
15 to 0
DW32 DW31 DW30
DW72 DW71 DW70
14
14
Initial Value
CS3
CS7
Table 7-21
Address
Caution
Access
13
13
Note
Bit name
DWk[2:0]
(4)
12
12
DWCn - Data wait control registers
The 16-bit DWCn registers control the number of wait states after the first
access cycle (T1). Each chip select area is controlled separately. A maximum
of seven data wait states is possible.
This register can be read/written in 16-bit units.
DWC0: FFFF F484
DWC1: FFFF FFE0
7777
each chip select area.
DWCn registers contents
1.
2.
To initialize an external memory area after a reset, this register has to be set.
Do not access external devices before initialization is finished. Do not change
this register while an external device is accessed.
Preliminary User’s Manual U17566EE1V2UM00
11
11
0
0
For access to internal memory, programmable waits are not carried out.
During page ROM on-page access, wait control is performed according to
PRC register setting.
H
: After system setup, by default, seven data wait states are inserted for
Function
Sets the number of wait states after the first access cycle (T1) for each chip
select area.
DW22 DW21 DW20
DW62 DW61 DW60
10
10
CS2
CS6
DWk[2:0]
000
001
010
011
111
9
9
...
H
H
B
B
B
B
B
8
8
Number of inserted wait states
No wait state inserted
1 wait state
2 wait states
3 wait states
...
7 wait states
7
0
7
0
DW12 DW11 DW10
DW52 DW51 DW50
6
6
Bus and Memory Control (BCU, MEMC)
CS1
CS5
5
5
4
4
3
0
3
0
DW02 DW01 DW00
DW42 DW41 DW40
2
2
CS0
CS4
1
1
0
0
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