upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 814

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 22
a)
814
LCDC03
0
0
0
1
1
0
0
0
0
The frequency of the LCD clock is determined in the clock generator.
Possible frame
frequencies
Table 22-5
LCDC02
1
1
1
0
0
0
0
0
0
LCDC01
Table 22-5 lists the possible frame frequencies. The values in Table 22-5 are
only examples. Check “Clock Generator“ on page 129 for details.
Selection of the following LCD clocks is provided:
• LCDC0.LCDC0[3:2] = 00
• LCDC0.LCDC0[3:2] = 01
• LCDC0.LCDC0[3:2] = 10
Example settings for frame frequency and duty cycle
Preliminary User’s Manual U17566EE1V2UM00
0
1
1
0
0
0
0
0
1
LCD clock = LCDCLK = f
– f
– d = divider
LCD clock = SPCLK7 = SPCLK0 / 2
LCD clock = SPCLK9 = SPCLK0 / 2
It can be selected from f
(200 KHz).
LCDCLK is gained by dividing the root clock by d. Divider d can be
selected from 2
0
= root clock for LCDCLK
LCDC00
1
0
1
0
1
0
1
1
0
LCD clock
SPCLK7 = 125 KHz
SPCLK7 = 125 KHz
SPCLK7 = 125 KHz
SPCLK9 = 31.25 KHz
SPCLK9 = 31.25 KHz
LCDCLK = 32.768 KHz
(with f
and d = 2
LCDCLK = 32.768 KHz
LCDCLK = 100 KHz
(with f
and d = 2
LCDCLK = 100 KHz
0
to 2
0
0
= f
= f
7
0
1
.
sub
ring
)
)
B
B
B
0
a
/ d, with
main
(4 MHz), f
7
9
= 125 KHz
= 31.25 KHz
LCD Controller/Driver (LCD-C/D)
sub
(32.768 KHz), or f
Duty cycle
frequency
977 Hz
488 Hz
244 Hz
488 Hz
244 Hz
512 Hz
256 Hz
781 Hz
391 Hz
ring
frequency
244 Hz
122 Hz
122 Hz
128 Hz
195 Hz
Frame
64 Hz
98 Hz
61 Hz
61 Hz