upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 138

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

a)
Chapter 4
138
Bit position
Before enabling PLLEN or SCEN, make sure that the main oscillator is running and has settled (see also CG-
STAT register). The CPU must operate on the sub, ring or main oscillator clock when setting PLLEN or SCEN
to 1. Before selecting the SSCG / PLL outputs as clock sources for peripherals, ensure by software that the
SSCG / PLL stabilization time has elapsed.The stabilization times are defined in the Electrical Target Specifi-
cation.
7
6
5
3
Initial Value
Table 4-4
Address
Access
4.2.1 General clock generator registers
Bit name
PLLEN
SCEN
PERIC
DEN
(1)
a
a
The general Clock Generator registers control and reflect the operation of the
Clock Generator.
CKC - Clock Generator control register
The 8-bit CKC register controls the clock management.
This register can be read/written in 8-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to “PHCMD - Command protection register” on page 140 for
details.
FFFF F822
00
a)
CKC register contents
Preliminary User’s Manual U17566EE1V2UM00
PLLEN
H
R/W
. The register is initialized by any reset.
7
Function
PLL enable:
It is not possible to clear this bit by writing to the register. The bit is automatically
cleared in WATCH, Sub-WATCH, or STOP mode.
SSCG enable:
It is not possible to clear this bit by writing to the register. The bit is automatically
cleared in WATCH, Sub-WATCH, or STOP mode.
SSCG dithering mode enable:
DEN must not be toggled while SCEN is 1.
Clock source selection for PCLK0/1:
This bit is automatically cleared in WATCH, Sub-WATCH, or STOP mode.
These bits may be written, but write is ignored.
0: PLL disabled.
1: PLL on.
0: SSCG disabled.
1: SSCG on.
0: SSCG uses fixed multiplication factor determined by SCFC0, SCFC1
1: SSCG is in dithering mode. The base frequency, determined by the registers
0: Main oscillator is clock source for peripheral clocks PCLK0, PCLK1.
1: PLL (x4) is clock source for peripheral clocks PCLK0, PCLK1.
SCFC0, SCFC1, is modulated according to the setup of register SCFMC.
SCEN
H
R/W
.
6
DEN
R/W
5
R
4
0
a
PERIC
R/W
3
R
2
0
a
R
Clock Generator
1
0
a
R
0
0
a