upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 265
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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CSC0
CSC1
Bus and Memory Control (BCU, MEMC)
CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00
CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60 CS73 CS72 CS71 CS70
15
15
14
14
Initial Value
CS3
CS4
Address
Caution
Access
13
13
(3)
12
12
CSCn - Chip area select control registers
The 16-bit registers CSC0 and CSC1 assign the chip select signals CS0 to
CS3 and CS4 to CS7 to memory blanks (see also “Memory banks and chip
select signals” on page 252). If a bit in CSCn is set, access to the
corresponding memory bank will generate the corresponding chip select signal
and activate the Memory Controller.
If several chip select signals are assigned to identical memory areas, a priority
control rules the generation of the signals (refer to “Chips select priority
control” on page 255).
These registers can be read/written in 16-bit units.
CSC0: FFFF F060
CSC1: FFFF F062
2C11
Thess registers must be initialized as described in Table 7-13 and Table 7-14.
The register contents in Table 7-11 and Table 7-12 read as follows:
• CSkm = 0: Corresponding chip select signal is not active during access to
• CSkm = 1: Corresponding chip select signal is active during access to
To initialize an external memory area after a reset, registers CSCn have to be
set. Do not change these registers after initialization. Do not access external
devices before initialization is finished.
Preliminary User’s Manual U17566EE1V2UM00
memory bank.
memory bank.
11
11
H
10
10
CS2
CS5
9
9
H
H
8
8
7
7
6
6
CS1
CS6
5
5
4
4
3
3
2
2
CS0
CS0
Chapter 7
1
1
0
0
265
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