upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 201
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
- Current page: 201 of 930
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Interrupt Controller (INTC)
Figure 5-4
Caution
5.2.2 Restore
Note
1
(1)
(2)
NMI0
Execution is restored from the non-maskable interrupt (NMI0) processing by
the RETI instruction.
When the RETI instruction is executed, the CPU performs the following
processing, and transfers control to the address of the restored PC.
<1> Restores the values of the PC and the PSW from FEPC and FEPSW,
<2> Transfers control back to the address of the restored PC and PSW.
Figure 5-4 illustrates how the RETI instruction is processed.
RETI instruction processing
When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction
during non-maskable interrupt processing, in order to restore the PC and PSW
correctly during recovery by the RETI instruction, it is necessary to set
PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction
immediately before the RETI instruction.
The solid line indicates the CPU processing flow.
NMIWDT
Restoring by RETI instruction is not possible. Perform a system reset after
interrupt servicing.
Preliminary User’s Manual U17566EE1V2UM00
Original processing restored
PC
PSW
respectively, because the EP bit of the PSW is 0 and the NP bit of the
PSW is 1.
RETI instruction
PSW.EP
PSW.NP
0
0
EIPC
EIPSW
1
PC
PSW
FEPC
FEPSW
Chapter 5
201
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