upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 392
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
- Current page: 392 of 930
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Chapter 11
392
External trigger input
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
(TIPn0 pin input)
16-bit counter
TPnCE bit
FFFFH
0000H
(3)
Operation timing in one-shot pulse output mode
(a) Note on rewriting TPnCCRm register
Preliminary User’s Manual U17566EE1V2UM00
To change the set value of the TPnCCRm register to a smaller value, stop
counting once, and then change the set value.
If the value of the TPnCCRm register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
When the TPnCCR0 register is rewritten from D
register from D
register is rewritten when the count value of the 16-bit counter is greater
than D
the count value is greater than D
reflected as soon as the register has been rewritten and compared with the
count value. The counter counts up to FFFFH and then counts up again
from 0000H. When the count value matches D
INTTPnCC1 signal and asserts the TOPn1 pin. When the count value
matches D
TOPn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active
period different from that of the one-shot pulse that is originally expected.
Delay
(D
11
10
D
)
10
and less than D
Active level width
(D
01
00
D
, the counter generates the INTTPnCC0 signal, deasserts the
− D
00
10
10
to D
+ 1)
D
10
11
D
Delay
(D
00
where D
10
D
10
)
10
Active level width
(D
and if the TPnCCR0 register is rewritten when
00
D
− D
00
00
01
10
> D
+ 1)
and less than D
16-bit Timer/Event Counter P (TMP)
01
and D
D
10
Delay
(10000H + D
10
11
00
, the counter generates the
D
> D
00
to D
00
11
, each set value is
, if the TPnCCR1
01
11
and the TPnCCR1
)
D
D
D
Active level width
(D
11
11
01
D
01
01
− D
11
+ 1)
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