upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 155

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
Bit position
2 to 0
7
Initial Value
Table 4-16
Address
FOCKS[1:0]
Access
Bit name
FOSOS,
FOEN
Note
(4)
FCC - FOUTCLK control register
The 8-bit FCC register configures the output clock FOUTCLK that can be used
for external devices.
This register can be read/written in 8-bit or 1-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to “PHCMD - Command protection register” on page 140 for
details.
FFFF F834
00
a)
FCC register contents
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
Function
Output clock FOUTCLK enable:
Clock source selection for FOUTCLK:
Caution:
H
FOEN
R/W
0: FOUTCLK is disabled.
1: FOUTCLK is enabled.
. The register is initialized by any reset.
FOUTCLK is not influenced by stand-by modes of the microcontroller. It
runs as long as it is enabled and the selected clock source operates.
Application software must stop FOUTCLK by clearing the FOEN bit to
minimize power consumption in stand-by modes.
There is an upper frequency limit for the output buffer of the FOUTCLK
function. Do not select a frequency higher than the maximum output buffer
frequency. Please refer to the Electrical Target Specification for the
frequency limit.
7
These bits must not be altered.
FOSOS
X
X
X
0
1
H
.
Do not specify the sub oscillator, if the sub oscillator is not enabled or not
connected.
R/W
0
6
a
FOCKS1 FOCKS0 Clock source
0
0
1
1
1
R/W
0
5
a
0
1
0
1
1
R/W
0
4
a
Main oscillator
SSCG
PLL
Ring oscillator
Sub oscillator
R
3
0
FOSOS
R/W
2
FOCKS1
R/W
1
Chapter 4
FOCKS0
R/W
0
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