upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 224
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
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Chapter 5
224
Figure 5-14
5.6.2 Debug trap
(1)
The debug trap is an exception that can be acknowledged every time and is
generated by execution of the DBTRAP instruction.
When the debug trap is generated, the CPU performs the following processing.
Operation
When the debug trap is generated, the CPU performs the following processing,
transfers control to the debug monitor routine, and shifts to debug mode.
(1)
(2)
(3)
(4)
Figure 5-14 illustrates the processing of the debug trap.
Debug trap processing
Preliminary User’s Manual U17566EE1V2UM00
Saves the restored PC to DBPC.
Saves the current PSW to DBPSW.
Sets the NP, EP and ID bits of the PSW.
Sets the handler address (00000060H) corresponding to the debug trap
to the PC and transfers control.
CPU processing
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Exception processing
DBTRAP instruction
Interrupt Controller (INTC)
restored PC
PSW
1
1
1
00000060H
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