upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 443
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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16-bit Multi-Purpose Timer G (TMG)
position
7, 6
3, 1
2, 0
Bit
Table 13-4
Bit name
CCSGn5
CCSGn0
TMGnxE
CLRGnx
TMGMn register contents (2/2)
Preliminary User’s Manual U17566EE1V2UM00
Function
Specifies the mode of the TMGn0 (TMGn1)(CCSGn5 for TMGn1, CCSGn0 for
TMGn0):
Caution:
Specifies software clear for TMGnx
Note: TMGnx starts 1 peripheral-clock after this bit is set this bit is not readable
Specifies TMGnx count operation enable/disable
Note: 1. the counter needs at least 1 peripheral-clock (
0: Free-run mode for TMGn1 (TMGn0), GCCn5 (GCCn0) in capture mode (an
1: Match and Clear mode of the TMGn1 (TMGn0), GCCn5 (GCCn0) in compare
0: Continue TMGnx operation
1: Clears (0) the count value of TMGnx, the corresponding TOGnx is deactivated.
0: Stop count operation the counter holds the immediate preceding value the
1: Enable count operation
detected edge at Pin TIGn5 (TIGn0) stores the value of TMGn1 (TMGn0) in
GCCn5 (GCCn0) and an interrupt INTCCGn5 (INTCCGn0) is output)
mode (when the data of GCCn5 (GCCn0) match the count value of the TMGn1
(TMGn0), the counter is cleared and the interrupt INTCCGn5 (INTCCGn0)
occurs)
corresponding TOGnx is deactivated
(always read 0)
2. the counter needs at least 4 peripheral-clocks (
When the POWERn bit is set, the rewriting of this bits are prohibited!
Simultaneously writing with the POWERn bit is allowed.
f
SPCLK0
f
SPCLK0
) to stop
) to start
Chapter 13
443
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