upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 350

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 11
350
Bit position
3 to 2
1 to 0
Initial Value
Table 11-6
Address
Caution
Access
Bit name
TPnIS[3:2]
TPnIS[1:0]
(4)
TPnIOC1 - TMPn I/O control register 1
The TPnIOC1 register is an 8-bit register that controls the valid edge of the
capture trigger input signals (TIPn0, TIPn1 pins).
This register can be read/written in 8-bit or 1-bit units.
<base> + 3
00
TPnIOC1 register contents
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
H
Rewrite the TPnIS3 to TPnIS0 bits when the TPnCTL0.TPnCE bit = 0. (The
same value can be written when the TPnCE bit = 1.) If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then set the bits again.
The TPnIS3 to TPnIS0 bits are valid only in the free-running timer mode and
the pulse width measurement mode. In all other modes, a capture operation
is not possible.
R/W
. This register is initialized by any reset.
7
0
Function
Capture trigger input signal (TIPn1 pin) valied edge setting:
Capture trigger input signal (TIPn0 pin) valied edge setting:
TPnIS3
TPnIS1
H
0
0
1
1
0
0
1
1
R/W
6
0
TPnIS2
TPnIS0
R/W
5
0
0
1
0
1
0
1
0
1
Capture trigger valid edge of TIPn1
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger valid edge of TIPn0
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
R/W
4
0
16-bit Timer/Event Counter P (TMP)
TPnIS3
R/W
3
TPnIS2
R/W
2
TPnIS1
R/W
1
TPnIS0
R/W
0