upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 360

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 11
360
TPnIOC0
TPnCTL1
0
Note
0
0
(b) TMPn control register 1 (TPnCTL1)
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn counter read buffer register (TPnCNT)
(e) TMPn capture/compare register 0 (TPnCCR0)
(f) TMPn capture/compare register 1 (TPnCCR1)
TMPn I/O control register 1 (TPnIOC1), TMPn I/O control register 2
(TPnIOC2), and TMPn option register 0 (TPnOPT0) are not used in the interval
timer mode.
Preliminary User’s Manual U17566EE1V2UM00
TPnEST
0
By reading the TPnCNT register, the count value of the 16-bit counter can
be read.
If the TPnCCR0 register is set to D
Interval = (D
Usually, the TPnCCR1 register is not used in the interval timer mode.
However, the set value of the TPnCCR1 register is transferred to the CCR1
buffer register. A compare match interrupt request signal (INTTPnCC1) is
generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
Therefore, mask the interrupt request by using the corresponding interrupt
mask flag (TPnCCMK1).
0
TPnEEE
0
0
0
+ 1) × Count clock cycle
TPnOL1
0
0/1
TPnOE1 TPnOL0
0
0/1
TPnMD2 TPnMD1 TPnMD0
0/1
0
0
, the interval is as follows.
16-bit Timer/Event Counter P (TMP)
TPnOE0
0/1
0
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level
0
0, 0, 0:
Interval timer mode