upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 390

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 11
390
TPnIOC0
TPnIOC2
• When TPnOL1 bit = 0
TOPn1 pin output
16-bit counter
0
0
Note
0
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn I/O control register 2 (TPnIOC2)
(e) TMPn counter read buffer register (TPnCNT)
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0)
are not used in the one-shot pulse output mode.
Preliminary User’s Manual U17566EE1V2UM00
0
The value of the 16-bit counter can be read by reading the TPnCNT
register.
If D
active level width and output delay period of the one-shot pulse are as
follows.
Active level width = (D
Output delay period = D
0
0
0
is set to the TPnCCR0 register and D
0
0
TPnOL1
TPnEES1
0/1
1
0/1
- D
1
× Count clock cycle
0
TPnOE1 TPnOL0
+ 1) × Count clock cycle
TPnEES0 TPnETS1 TPnETS0
• When TPnOL1 bit = 1
0/1
0/1
TOPn1 pin output
16-bit counter
0/1
16-bit Timer/Event Counter P (TMP)
0/1
TPnOE0
1
0/1
to the TPnCCR1 register, the
0/1
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level while
operation of TOPn0 pin is disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Specifies active level of
TOPn1 pin output
0: Active-high
1: Active-low
Select valid edge of
external trigger input
Select valid edge of
external event count input