upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 530

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 16
530
Error flag
UAnPE
UAnFE
UAnOVE
Table 16-6
Caution
16.5.8 Reception errors
16.5.9 Parity types and operations
Note
Reception error
Parity error
Framing error
Overrun error
(1)
Errors during a receive operation are of three types: parity errors, framing
errors, and overrun errors. Data reception result error flags are set in the
UAnSTR register and a reception error interrupt request signal (INTUAnRE) is
output when an error occurs.
It is possible to ascertain which error occurred during reception by reading the
contents of the UAnSTR register.
Clear the reception error flag by writing 0 to it after reading it.
Reception error causes
Note that even in case of a parity or framing error, data is transferred from the
receive shift register to the receive data register UAnRX. Consequently the
data from UAnRX must be read. Otherwise an overrun error UAnSTR.UAnOVE
will occur at reception of the next data.
In case of an overrun error, the receive shift register data is not transferred to
UAnRX, thus the previous data is not overwritten.
When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the
UAnCTL0 register to 00.
The parity bit is used to detect bit errors in the communication data. Normally
the same parity is used on the transmission side and the reception side.
In the case of even parity and odd parity, it is possible to detect odd-count bit
errors. In the case of 0 parity and no parity, errors cannot be detected.
Even parity
• During transmission
• During reception
Preliminary User’s Manual U17566EE1V2UM00
The number of bits whose value is “1” among the transmit data, including
the parity bit, is controlled so as to be an even number. The parity bit values
are as follows.
– Odd number of bits whose value is “1” among transmit data:1
– Even number of bits whose value is “1” among transmit data:0
The number of bits whose value is “1” among the reception data, including
the parity bit, is counted, and if it is an odd number, a parity error is output.
Cause
Received parity bit does not match the setting
Stop bit not detected
Reception of next data completed before data was read from
receive buffer
Asynchronous Serial Interface (UARTA)