upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 321
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
- Current page: 321 of 930
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DMA Controller (DMAC)
a)
a)
Reset value
IFCn2
DTFRn
0
0
0
0
1
1
1
1
R/W
The default value “0” of this bit must not be changed!
µPD70F3425, µPD70F3424 only
Addresses
IFCn1
Caution
0
0
1
1
0
0
1
1
R/W
8.3.7 DTFRn - DMA trigger source select register
DRQn
Note
7
0
Note
IFCn0
The 8-bit DMA trigger source selection registers are used to control the DMA
transfer triggers for the individual DMA channels. These triggers initiate DMA
transfer requests received from built-in peripheral hardware.
Interrupt signals are used as DMA transfer requests.
These registers support read/write in 8-bit units or bit-wise.
DTFR0: FFFF FE00H
DTFR1: FFFF FE02H
DTFR2: FFFF FE04H
DTFR3: FFFF FE06H
DRQn and DOFLn are set by hardware.
DRQn and DOFLn can be reset by software. Setting these bits by software is
not possible. A “0” must be written to the respective bit location to reset these
bits.
The bits DTFRn.IFCn[2:0] select the interrupts to be used as DMA trigger
sources according to the following table
If the DMA trigger source is changed by modifying DTFRn.IFCn[2:0] bits while
DMA channel n is active, a DMA request may be set accidentally.
Proceed in any of the two ways when changing the DMA trigger source:
1. Disable the DMA channel n by DCHCn.ENn = 0 before changing the DMA
Preliminary User’s Manual U17566EE1V2UM00
0
1
0
1
0
1
0
1
R/W
DOFLn
trigger source DTFRn.IFCn[2:0].
n
6
0
Note
INTTP0CC1
Channel 0
INTTZ0UV
INTCB1R
INTCB0R
INTUA0R
INTUA1R
INTCB1T
INTIIC0
DMACTn
0
R/W
5
0
R/W
0
4
0
INTTP1CC1
a
Channel 1
INTTZ0UV
INTCB2R
INTCB2T
INTUA0R
INTUA1R
INTCB0T
INTLCD
1
a
a
a
R/W
0
3
0
a
INTTG0CC1
Channel 2
INTTZ1UV
INTCB1R
INTCB0R
INTCB1T
INTUA0T
INTUA1T
INTIIC1
IFCn2
R/W
2
0
2
IFCn1
R/W
1
0
Channel 3
INTCB2R
INTTZ2UV
INTCB2T
INTCB0T
INTUA0T
INTUA1T
INTLCD
INTAD
Chapter 8
3
IFCn0
R/W
0
0
a
a
a
321
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