upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 273

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upd70f3422gj-gae-qs-ax

Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
Bus and Memory Control (BCU, MEMC)
AC71 AC70 AC61 AC60 AC51 AC50 AC41 AC40 AC31 AC30 AC21 AC20 AC11 AC10 AC01 AC00
Bit position
15
15 to 0
CS7
14
Initial Value
Table 7-20
Address
Caution
Access
13
Note
CS6
Bit name
ACk[1:0]
(3)
12
ASC - Address setup wait control register
The 16-bit ASC register controls the number of wait states between address
setup and the first access cycle (T1). Each chip select area is controlled
separately. A maximum of three address setup wait states is possible.
Address setup wait states can be inserted when accessing
• SRAM
• page ROM
This register can be read/written in 16-bit units.
FFFF F48A
FFFF
inserted for each chip select area.
ASC register contents
1.
2.
To initialize an external memory area after a reset, this register has to be set.
Do not access external devices before initialization is finished. Do not change
this register while an external device is accessed.
Preliminary User’s Manual U17566EE1V2UM00
11
During address setup wait, the external wait function (WAIT pin) is
disabled.
For access to internal memory, the setting of register ASC is neglected. No
wait states are inserted after address setup.
CS5
H
: After system setup, by default, three address setup wait states are
Function
Sets the number of address setup wait states for each chip select area.
10
H
ACk[1:0]
9
00
01
10
11
CS4
B
B
B
B
8
7
Wait states inserted after address setup
No wait state inserted
1 wait state
2 wait states
3 wait states
CS3
6
5
CS2
4
3
CS1
2
Chapter 7
1
CS0
0
273

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