upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 180

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 4
180
Note
In this example, maskable interrupts are permitted to leave the power save
mode.
Be aware of the following notes when entering power save mode using the
above sequence:
1.
2.
3.
4.
Preliminary User’s Manual U17566EE1V2UM00
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
It is recommended to disable maskable interrupt acknowledgement in
general by the “di” instruction (step 3.) to prevent any pending interrupt
from being served during the power save mode set-up procedure. This
makes it also possible to completely control the process after wake-up,
since no pending interrupt will be unintentional acknowledged. Before
enabling interrupt acknowledgement by the “ei” instruction (step 16.) after
wake-up, all unwanted interrupts can be discarded by setting xxIC.xxIF = 0
(step 15.).
Since the wake-up capability of the unmasked wake-up interrupts is not
affected by “di”, such interrupts shall be masked (step 1.) by
IMRm.xxMK = 1.
The store instruction to PRCMD will not allow to acknowledge any interrupt
until processing of the subsequent instruction is complete. That means, an
interrupt will not be acknowledged before the store to PSC. This
presupposes that both store instructions are performed consecutively, as
shown in the above example.
If another instruction is placed between steps 7 and 8, an interrupt request
may be acknowledged in between, and the power save mode may not be
entered.
However if the “di” instruction was executed before (step 3.) none interrupt
will be acknowledged anyway.
At least 5 “nop” instructions must follow the power down mode setting, that
means after the write to PSC. The microcontroller requires this time to
enter power down mode.
The data written to the PRCMD register must be the same data that shall
be written to the write-protected register afterwards.
The above example ensures this method, since the contents of r10 is first
written to PRCMD and then immediately to PSC.
// xxIC.xxMK = 0
// xxIC.xxMK = 1
di
mov
st.b
mov
st.b
st.b
nop
nop
nop
nop
nop
// xxIC.xxIF = 0
ei
0x02,r10
10,PSM[r0]
0x62,r10
r10,PRCMD[r0]
r10,PSC[r0]
// PSM.PSM[1:0] = 10B: WATCH mode
// mask all none wake-up interrupts
// unmask all wake-up interrupts
// enable write to PSC
// wake up by maskable interrupts
// and enter power save mode
// after wake-up
// discard all unwanted pending interrupts
Clock Generator