upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 519

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upd70f3422gj-gae-qs-ax

Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
Asynchronous Serial Interface (UARTA)
16.5.1 Data format
16.5 Operation
(1)
Start
Start
bit
bit
Full-duplex serial data reception and transmission is performed.
As shown in the figures below, one data frame of transmit/receive data
consists of a start bit, character bits, parity bit, and stop bit(s).
Specification of the character bit length within 1 data frame, parity selection,
specification of the stop bit length, and specification of MSB/LSB-first transfer
are performed using the UAnCTL0 register.
Moreover, control of UART output/inverted output for the TXDAn bit is
performed using the UAnOPT0.UAnTDL bit.
• Start bit..........................1 bit
• Character bits................7 bits/8 bits
• Parity bit ........................Even parity/odd parity/0 parity/no parity
• Stop bit ..........................1 bit/2 bits
UARTA transmit/receive data format
(a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H
(b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H
Preliminary User’s Manual U17566EE1V2UM00
D0
D7
D1
D6
D2
D5
D4
D3
1 data frame
1 data frame
D4
D3
D5
D2
D6
D1
D0
D7
Parity
Parity
bit
bit
Stop
Stop
bit
bit
Chapter 16
519

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