upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 261
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Bus and Memory Control (BCU, MEMC)
PA15
Bit Position
15
13 to 0
15
14
0
Initial Value
Table 7-7
Table 7-8
Address
PA13 PA12 PA11 PA10
Caution
Access
13
Bit Name
7.3.1 BCU registers
PA[13:0]
PA15
(1)
12
The following registers are part of the BCU. They define the usage of the
programmable peripheral I/O area (PPA), the data bus width, the endian format
of word data, and they control access to external devices.
BPC - Peripheral area selection control register
The 16-bit BPC register defines whether the programmable peripheral I/O area
(PPA) is used or not and determines the starting address of the PPA.
This register can be read/written in 16-bit units.
FFFF F064
0000
BPC register contents
Bit 14 must always be 0.
The base address PBA of the programmable peripheral area sets the start
address of the 16 KB PPA in a range of 256 MB. The 256 MB page is mirrored
16 times to the entire 32-bit address range.
The base address PBA is calculated by
Table 7-8 shows how the base address PBA of the programmable peripheral
area is assembled.
Address range of programmable peripheral area (16 KB)
Preliminary User’s Manual U17566EE1V2UM00
31
Function
Select usage of programmable peripheral I/O area (PPA).
Bits PA[13:0] specify bits 27 to 14 of the starting address of the PPA. The other bits
of the address are fixed to 0.
11
0
0
0
PBA = BPC.PA[13:0] x 2
0: PPA disabled
1: PPA enabled
H
…
…
…
…
…
10
H
28 27
0
0
0
PA9
9
PA8
8
BPC.PA[13:0]
BPC.PA[13:0]
BPC.PA[13:0]
PA7
14
7
…
…
PA6
6
PA5
5
PA4
14 13
4
1
0
0
PA3
3
…
…
…
…
PA2
…
2
1
1
0
0
PA1
Chapter 7
1
0
1
1
0
PA0
PBA
bit
0
261
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