upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 826

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 23
826
Access
Write
Read
Table 23-2
23.1.4 Interrupt generation
TCIS0 = 0
An interrupt is generated as soon as data is
transferred from LBDATA0 to the write buffer.
Then LBDATA0 is ready to accept next data.
The write buffer is filled whenever the external
bus interface is idle (no transfer in progress)
and data is available in LBDATA0.
An interrupt is generated as soon as the data is
available in the LBDATA0 or LBDATAR0
register.
Depending on the read access to LBDATA0
(byte, halfword or word) 1, 2, or 4 bytes are
transferred and placed in the LBDATA0 and
LBDATAR0 register. Finally, the interrupt is
generated in order to indicate that new data is
available.
(2)
(3)
Read operation
When the CPU or the DMA reads the LBDATA0 register, the read operation on
the LCD Bus Interface is started. If there is a write transfer in progress while
the LBDATA0 register shall be read, the read transfer is stalled and started
after the write transfer has completed.
The value read from the register is the data from the previous transfer.
Therefore, an initial dummy read operation is required to update the register.
As soon as the data of the actual transfer is available in the LBDATA0 register,
the busy flag LBCTL0.BYF0 is cleared and the data can be retrieved with the
next read operation. Successive reads from the LBDATA0 register provide the
desired data.
The read timing on the external bus interface is determined by the number of
wait cycles (LBWST0.WST0[4:0]), the cycle time (LBCYC0.CYC0[5:0]) and the
selected clock (LBCTL0.LBC0 and LBCTL00.LBC01).
Read operation without initiating a bus transfer
Data can be read from the LBDATAR0 register without initiating a new read
transfer via the LCD Bus Interface.
The read access to the LBDATAR0 register is useful when previous read
accesses to the LBDATA0 register have been performed and only the last
transferred data shall be read without starting a new LCD bus transfer.
An interrupt is generated on write and read accesses to the LCD Bus Interface.
Depending on the setting of the bit LBCTL0.TCIS0, the interrupt is generated
differently.
Controlling interrupt generation of the LCD Bus Interface
Preliminary User’s Manual U17566EE1V2UM00
TCIS0 = 1
An interrupt is generated as soon as the write
transfer via the bus interface has completed.
The transfer can consist of 1, 2, or 4 bytes
dependent on the access to LBDATA0.
An interrupt is generated as soon as the read
transfer via the bus interface has completed.
The transfer can consist of 1, 2, or 4 bytes
depending on the access to LBDATA0 or
LBDATAR0.
LCD Bus Interface (LCD-I/F)