upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 132

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 4
132
FOUTCLK
WCTCLK
WDTCLK
LCDCLK
WTCLK
4.1.2 Clock monitors
(4)
Calibration Timer. These clocks are directly derived from the oscillators and
bypass the PLLs.
The LCD Controller/Driver can be clocked by SPCLK7, SPCLK9, or LCDCLK.
This is the clock for the Watch Timer. It forms the time base for updating the
internal bookkeeping of daytime and calendar.
Note that LCDCLK and WTCLK have a common source and a fixed frequency
ratio (1/1 or 1/2).
This is the clock for the Watch Calibration Timer WCT. WCT is used in
conjunction with the Watch Timer for calibrating the time base during power
save modes by utilizing the main oscillator as the stable clock source.
WCTCLK can also be derived from PCLK1.
FOUTCLK is a clock signal that can be used for external devices. It is
connected to the pin FOUT and can provide almost any of the internal clock
frequencies (not phase-synchronized). FOUTCLK must be enabled before it
can be used.
This is the clock for the Watchdog Timer that is used for recovering from a
system deadlock. WDTCLK is available (and hence the Watchdog Timer
running) as long as the chosen clock source is active.
Stand-by control
In the block diagram, you find also boxes labelled “Standby”. These boxes
symbolize the switches that are used to disable circuits when the
microcontroller enters one of the various power save modes.
The following clocks are subject to automatic stand-by control:
CPU system clock, PCLK, SPCLK, IICLK.
The following clocks can be operating during power save modes (stand-by) as
long as their clock oscillator source is available:
FOUTCLK, LCDCLK, WTCLK, WCTCLK.
The microcontroller contains clock monitors to monitor the operation of the 4
MHz main oscillator and the 32 KHz sub oscillator. In case of malfunction,
these monitors can generate a system reset.
The monitors require that the built-in ring oscillator is active. For details see
“Operation of the Clock Monitors” on page 185.
Preliminary User’s Manual U17566EE1V2UM00
Clock Generator