upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 310

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 8
310
ADC
UARTA
CSIB
Peripheral Clock controller settings
Table 8-1
SCC = 00
SCC = 01
SCC = 03
SCPS.SPSPS[2:0] = 001
SSCG: 32 MHz
SCC = 03
SCPS.SPSPS[2:0] = 011
SSCG: 48 MHz
CKC.PERIC = 0
CKC.PERIC = 1
CKC.PERIC = 0
CKC.PERIC = 1
SCC = 00
SCC = 01
SCC = 03
SCPS.SPSPS[2:0] = 001
SSCG: 32 MHz
SCC = 03
SCPS.SPSPS[2:0] = 011
SSCG: 48 MHz
8.2 Peripheral and CPU Clock Settings
H
H
H
H
H
H
H
H
In order to ensure safe capture of DMA trigger signals from the involved
peripheral functions, a certain minimum relation between the operation clock of
the concerned peripheral function and the CPU system has to be regarded.
In the following table the minimum CPU system clock frequency f
for all peripheral functions operation clocks.
Peripheral functions and CPU system clocks for DMA transfers (1/2)
Preliminary User’s Manual U17566EE1V2UM00
B
B
B
B
Peripheral clock
via Baud Rate
Generator
SPCLK0
SPCLK0
SPCLK0
SPCLK0
SPCLK1
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
PCLK8
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
SPCLKn, PCLKn
configuration
MainOsc/16
MainOsc/32
MainOsc/64
MainOsc/16
MainOsc/2
MainOsc/4
MainOsc/8
MainOsc/2
MainOsc/4
MainOsc/8
f
f
MainOsc
MainOsc
MainOsc
MainOsc
MainOsc
MainOsc
SSCGPS
SSCGPS
f
f
Source
SSCGPS
SSCGPS
PLL/4
PLL/2
PLL/4
PLL/4
/2
/2
Input clock
min. 0.002
min. 0.002
min. 0.002
min. 0.002
DMA Controller (DMAC)
0.0625
max. 4
max. 8
max. 8
max. 8
[MHz]
0.125
0.250
0.25
0.5
0.5
16
16
12
4
4
8
4
2
1
4
8
4
2
1
VBCLK
Minimum
f
[MHz]
VBCLK
24.00
24.00
18.00
12.00
12.00
0.003
12.00
0.003
12.00
0.003
12.00
0.003
6.00
6.00
6.00
3.00
0.75
0.38
0.19
0.09
6.00
6.00
3.00
1.50
0.75
0.38
6.00
1.5
is given