upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 258

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 7
258
Table 7-4
Table 7-5
7.2.6 Boundary operation conditions
Note
(3)
(1)
(2)
Bus priority order
Bus access
The number of CPU clocks necessary for accessing each resource –
Number of bus access clocks
The microcontroller device has the following boundary operation conditions:
Program space
Instruction fetches from the internal peripheral I/O area are inhibited and yield
NOP operations.
If a branch instruction exists at the upper limit of the internal RAM area, a pre-
fetch operation (invalid fetch) that straddles over the internal peripheral I/O
area does not occur.
Data space
The microcontroller device is provided with an address misalign function.
By this function, data of any format (word: 32 bit, halfword: 16 bit, byte: 8 bit)
can be placed to any address in memory, even though the address is not
aligned to the data format (that means address 4n for words, address 2n for
halfwords).
• Unaligned halfword data access
• Unaligned word data access
Accessing data on misaligned addresses takes more than one bus cycle to
complete data read/write. Consequently, the bus efficiency will drop.
Preliminary User’s Manual U17566EE1V2UM00
Priority
High
Low
a)
b)
independent of the bus width – is as follows:
Bus cycle configuration
Instruction fetch
Operand data access
When the LSB of the address is A0 =1, two byte accesses are performed.
When the LSB of the address is A0 =1, two byte and one halfword accesses
are performed. In total it takes 3 bus cycles.
– When the LSBs of the address are A[1:0] =10
are performed.
In case of contention with data access, the instruction fetch from internal RAM
takes 2 clocks.
This is the minimum value.
Normal access
Branch
External bus cycle
DMA cycle
Operand data access
Instruction fetch
Internal RAM
Bus and Memory Control (BCU, MEMC)
1
1
1
a
External I/O
B
, two halfword accesses
Bus master
DMA Controller
CPU
CPU
3
–
–
b
External
memory
2
2
2
b
b
b