upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 157

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
Initial Value
Address
Access
4.2.4 Control registers for power save modes
(1)
The registers described in this section control the begin and end of the power
save modes IDLE, WATCH, Sub-WATCH, and STOP.
Please refer to “Power save mode activation” on page 179 for instructions and
an example on how to enter a power save mode.
PSM - Power save mode register
The 8-bit PSM register specifies the power save mode and controls the clock
generation after reset and Sub-WATCH mode release. In addition, it specifies
the source of the Watch Calibration Timer clock WCTCLK.
This register can be read/written in 8-bit or 1-bit units.
FFFF F820
08
Since the main oscillator is started by the internal firmware are reset, PSM
enters the user’s program with the setting 00
Preliminary User’s Manual U17566EE1V2UM00
H
. The register is initialized by any reset.
R
7
0
CMODE
H
R/W
.
6
R
5
0
R
4
0
OSCDIS
R/W
3
H
.
R
2
0
PSM1
R/W
1
Chapter 4
PSM0
R/W
0
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