upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 568

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 17
568
Caution
CBnRX register read
CBnOVE bit clear
Note
(CBnSTR)
(5)
Continuous reception
Set the CBnSCE bit to 1 in the initial setting.
In the master mode, the clock is output without limit when dummy data is read
from the CBnRX register. To stop the clock, execute the flow marked
above flowchart.
In the slave mode, malfunction due to noise during communication can be
prevented by executing the flow marked
Before resuming communication, set the CBnCTL0.CBnSCE bit to 1, and read
dummy data from the CBnRX register.
Preliminary User’s Manual U17566EE1V2UM00
Yes
CBnRX register dummy read
Initial setting (CBnCTL0
CBnCTL1 registers, etc.)
CBnRX register read
CBnRX register read
received last data?
INTCBnR bit = 1?
INTCBnR bit = 1?
CBnOVE bit = 1?
(start reception)
CBnSCE bit = 0
CBnSCE bit = 1
Is data being
(CBnCTL0)
(CBnCTL0)
(CBnSTR)
START
END
Yes
No
Yes
Yes
Note
,
No
No
No
in the above flowchart.
Clocked Serial Interface (CSIB)
CBnRX register read
in the