upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 322

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 8
322
2. Set the DMA request bit DTFRn.DRQn = 0 in parallel to changing
The following list details the functions of the individual DMA trigger sources
referenced in the above table.
• INTCB2R...INTCB0R
• INTCB2T…INTCB0T
• INTUA1R, INTUA0R
• INTUA1T, INTUA0T
• INTLCD
• INTIIC0, INTIIC1
Preliminary User’s Manual U17566EE1V2UM00
DMACTn
The receive interrupts of the Clocked Serial Interfaces CSIB2…CSIB0 are
used as DMA trigger sources. In case of a receive overflow condition no
DMA trigger will be issued. The receive error interrupt of the respective
CSIB INTCBnRE should be enabled to inform the application software about
the overflow condition.
The transmit interrupts of the Clocked Serial Interfaces CSIB2…CSIB0 are
used as DMA trigger sources.
The receive interrupts of the Asynchronous Serial Interfaces UARTA1 or
UARTA0 are used as DMA trigger sources.
In case of a receive overflow, or a framing or parity error condition, no DMA
trigger will be issued. The receive error interrupt INTUAnRE of the
respective UARTn should be enabled to inform the application software
about the error condition. These interrupts are also generated upon
reception of an SBF in LIN mode.
The transmit interrupts of the Asynchronous Serial Interfaces UARTA1 or
UARTA0 are used as DMA trigger sources.
The interrupt signal of the LCD Bus Interface macro is used to trigger the
DMA transfer.
The interrupts of the I
respective DMA channel.
DOFLn
DTFRn.IFCn[2:0], i.e. within the same write operation. Thus DTFRn must
be written in 8-bit access mode. Do not change DTFRn.IFCn[2:0] with
single-bit instructions.
DRQn
0
1
0
1
0
1
DMA request
No DMA transfer request is pending for channel n
DMA transfer request is pending for channel n
DMA request overflow
DMA transfer request overflow did not occur for channel n
DMA transfer request overflow occurred for channel n
DMA active count
DMACTn=0 must be set if internal RAM is not specified as source or
destination
DMACTn=1 must be set if internal RAM is specified as source or
destination
2
C Interfaces IIC0, IIC1 are used to trigger the
DMA Controller (DMAC)