upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 825

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

LCD Bus Interface (LCD-I/F)
Table 23-1
23.1.2 LCD Bus Interface access modes
23.1.3 Access types to the LBDATA0 register
Note
(1)
The external signals are listed in the following table.
LCD Bus Interface external connections
a)
The LCD Bus Interface can access the external LCD Controller/Driver in two
different modes. The mode is selected by the bit LBCTL0.IMD.
• mod80
• mod68
Access to the LBDATA0 register can be performed as:
• Byte access (8-bit)
• Halfword access (16-bit)
• Word access (32-bit)
1.
2.
Write operation
If there is no transfer in progress on the external bus interface, the new data is
immediately transferred to the external LCD controller. If there is a transfer in
progress, the new data is transferred after the current transfer has completed.
One, two or four bytes are transferred through the bus interface, depending on
how LBDATA0 was accessed (byte, halfword, or word).
The write timing on the external bus interface is determined by the number of
wait cycles (LBWST0.WST[4:0]), the cycle time (LBCYC0.CYC[5:0]) and the
selected clock (LBCTL0.LBC00 and LBCTL0.LBC01).
Preliminary User’s Manual U17566EE1V2UM00
Signal
name
DBWR
DBRD
DBD[7:0]
The control signals WR (DBWR) and RD (DBRD) are used to control the
external LCD Controller/Driver.
The control signals R/W (DBWR) and E (DBRD) are used to control the
external component.
The level of E depends on the setting of the bit LBCTL0.EL0:
– EL0=0: E is active high; data is read/written on the falling edge.
– EL0=1: E is active low; data is read/written on the rising edge.
Every access must address the base address of the LBDATA0 register.
Access to the individual bytes within the register is prohibited.
Before writing to or reading from the LBDATA0 register or reading the
LBDATAR0 register, always make sure that the busy flag LBCTL0.BYF is
zero.
The active level of E in mod68 is controlled by the bit LBCTL0.EL0.
I/O
O
O
I/O
Active
level
L
L
a
Reset
level
H
H
L
Function
mod80: Write strobe (WR)
mod68: Read/Write (R/W)
mod80: Read strobe (RD)
mod68: E strobe (E)
LCD data bus
Chapter 23
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