upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 594

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
594
SDAn
SCLn
Figure 18-5
Figure 18-6
18.6.1 Start condition
Start
condition
Address
1 to 7
condition”, “data”, and “stop condition” output via the I
is shown below.
I
The master device outputs the start condition, slave address, and stop
condition.
The acknowledge signal (ACK) can be output by either the master or slave
device (normally, it is output by the device that receives 8-bit data).
The serial clock (SCLn) is continuously output by the master device. However,
in the slave device, the SCLn pin’s low-level period can be extended and a wait
can be inserted.
A start condition is met when the SCLn pin is high level and the SDAn pin
changes from high level to low level. The start condition for the SCLn and
SDAn pins is a signal that the master device outputs to the slave device when
starting a serial transfer. The slave device can defect the start condition.
Start condition
A start condition is output when the IICCn.STTn bit is set (1) after a stop
condition has been detected (IICSn.SPDn bit = 1). When a start condition is
detected, the IICSn.STDn bit is set (1). By setting IICCN.STTn=1 the master
device will also cancel its own wait status.
Preliminary User’s Manual U17566EE1V2UM00
2
C bus serial data transfer timing
R/W
8
ACK
9
SDAn
SCLn
1 to 7
Data
H
8
ACK
9
1 to 7
Data
8
2
C bus’s serial data bus
ACK
9
Stop
condition
I
2
C Bus (IIC)