upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 151

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
Bit position
6 to 4
Write protection
2, 0
7
3
Table 4-13
WDTSEL0
Bit name
WPS[2:0]
SOSCW,
SOSTP
ROSTP
WCC register contents
Write protection of this register is achieved in two ways:
• The register can be written only once after Power-On-Clear reset or external
• The register is protected by a special sequence via the PHCMD register.
If a write is correctly performed by the special sequence after the register has
already once been written successfully PHS.PRERR remains 0, though the
write has been ignored.
PHS.PRERR shows violations of the special sequence only. It does not reflect
attempts to write the register more than once after reset.
Preliminary User’s Manual U17566EE1V2UM00
RESET.
A fail of a write by the special sequence is reflected by PHS.PRERR = 1.
Function
Sub oscillator STOP mode control
WDT clock divider selection:
Ring oscillator stop control:
Watchdog Timer clock source selection:
By default, the sub oscillator is disabled in STOP mode (see bit SOSTP). If SOSTP
is 1, choose main or ring oscillator before entering STOP mode.
Caution:
1: Sub oscillator will stop when STOP mode is entered.
0: Sub oscillator will not stop when STOP mode is entered.
1: Ring oscillator stops if WATCH, Sub-WATCH or STOP mode is entered
0: Ring oscillator always operates
SOSCW
WPS2
0
0
0
0
1
1
1
1
0
1
0
1
Do not specify the sub oscillator, if the sub oscillator is not enabled or
not connected.
WDTSEL0
WPS1
0
0
1
1
0
0
1
1
0
0
1
1
WDT clock source
Ring oscillator
Sub oscillator
Main oscillator
Setting prohibited
WPS0
0
1
0
1
0
1
0
1
Clock divider setting
1
1 / 2
1 / 4
1 / 8
1 / 16
1 / 32
1 / 64
1 / 128
Chapter 4
151