upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 730
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 19
730
19.12.2 CAN stop mode
Caution
(1)
(2)
(3)
The CAN stop mode can be used to set the CAN Controller to stand-by mode
to reduce power consumption. The CAN module can enter the CAN stop mode
only from the CAN sleep mode. Release of the CAN stop mode puts the CAN
module in the CAN sleep mode.
The CAN stop mode can only be released by writing 01B to the
CnCTRL.PSMODE1 and CnCTRL.PSMODE0 bits and not by a change in the
CAN bus state. No message is transmitted even when transmission requests
are issued or pending.
Entering CAN stop mode
A CAN stop mode transition request is issued by writing 11B to the PSMODE1
and PSMODE0 bits.
A CAN stop mode request is only acknowledged when the CAN module is in
the CAN sleep mode. In all other modes, the request is ignored.
To set the CAN module to the CAN stop mode, the module must be in the CAN
sleep mode. To confirm that the module is in the sleep mode, check that the
PSMODE1 and PSMODE0 bits = 01B, and then request the CAN stop mode. If
a bus change occurs at the CAN reception pin (CRXDn) while this process is
being performed, the CAN sleep mode is automatically released. In this case,
the CAN stop mode transition request cannot be acknowledged.
Status in CAN stop mode
The CAN module is in one of the following states after it enters the CAN stop
mode.
• The internal operating clock is stopped and the power consumption is
• To wake up the CAN module from the CPU, data can be written to the
• The CANn module registers can be read, except for the CnLIPT, CnRGPT,
• The CANn message buffer registers cannot be written or read.
• An initialization mode transition request is not acknowledged and is ignored.
Releasing CAN stop mode
The CAN stop mode can only be released by writing 01B to the PSMODE1
and PSMODE0 bits.
When the initialization mode is requested while the CAN module is in the CAN
stop mode, that request is ignored; the CPU has to release the stop mode and
subsequently CAN sleep mode before entering the initialization mode.
Preliminary User’s Manual U17566EE1V2UM00
minimized.
PSMODE1 and PSMODE0 bits, but nothing can be written to other CANn
module registers or bits.
CnLOPT, and CnTGPT registers.
CAN Controller (CAN)
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