upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 843

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Sound Generator (SG)
Figure 24-2
Tone signal
PWM signal,
duty cycle 66 %
Composite
signal
Analog
audio signal
24.1.2 Principle of operation
Note
Note
(1)
(2)
The software-controlled registers SG0FL, SG0FH, and SG0PWM are
equipped with hardware buffers. The Sound Generator operates on these
buffers.
This approach eliminates audible artifacts, because the buffers are only
updated in synchronization with the generated tone waveform.
This section provides an overview. For details please refer to “Sound
Generator Operation“ on page 849.
Generation of the tone frequency
The tone frequency is determined by two counters and their associated
compare register values. Two counters are necessary to keep the tone pulse
and the PWM signal synchronized.
The first counter (SG0FL) provides the input to the second (SG0FH) and also
to the PWM. It is used to keep the PWM frequency outside the audio range
(above 30 KHz) and within the signal bandwidth of the external sound system
(usually below 64 KHz). Its match value defines also the 100 % volume level.
The second counter (SG0FH) generates the tone frequency (245 Hz to
6 KHz).
If the target values of the counters SG0FL/SG0FH are changed to generate a
different tone frequency, the volume register SG0PWM has to be adjusted to
keep the same volume.
Generation of the volume information
The volume information (the “amplitude” of the audible signal) is provided as a
high-frequency PWM signal. In composite mode, the PWM signal is ANDed
with the tone signal, as illustrated in the following figure.
Generation of the composite output signal
After low-pass filtering, the analog signal amplitude corresponds to the duty
cycle of the PWM signal. Low-pass filtering (averaging) is an inherent
characteristic of a loudspeaker system.
The duty cycle can vary between 0 % and 100 %. Its generation is controlled
by the counter register SG0FL and the volume register SG0PWM.
Preliminary User’s Manual U17566EE1V2UM00
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Chapter 24
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