upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 329

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upd70f3422gj-gae-qs-ax

Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
DMA Controller (DMAC)
DMA Transfer
DMA Transfer
DMA Transfer
DMA Transfer
Request CH0
Request CH1
Request CH2
Request CH3
DMA Transfer
DMA Transfer
Request CH0
Request CH3
Figure 8-6
Figure 8-7
CPU
Note
Note
CPU
CPU
CPU
Figure 8-6 shows DMAC transfers in single transfer mode in which a higher
priority DMA transfer request is generated. DMA channels 0 to 2 are used for a
block transfer and channel 3 is used for a single transfer.
Single transfer example 2
The bus is always released
Figure 8-7 shows a DMA transfer example in single transfer mode in which a
lower priority DMA transfer request is generated within one clock after the end
of a single transfer. DMA channels 0 and 3 are used for the single transfer
example. When two DMA transfer request signals are activated at the same
time, the two DMA transfers are performed alternately.
Single transfer example 3
The bus is always released
Preliminary User’s Manual U17566EE1V2UM00
CPU DMA3 CPU
DMA0 CPU DMA0
Note
Note
Note
CPU
DMA0
DMA channel 0
terminal count
DMA3
DMA0
Note
CPU DMA0
Note
CPU DMA1
Note
DMA channel 1
CPU
terminal count
DMA channel 3
terminal count
DMA1
DMA3
Note
Note
CPU
CPU DMA0
DMA2
DMA channel 2
terminal count
Note
CPU
DMA2 CPU DMA3
DMA0 CPU DMA0
Note
Note
DMA channel 0
terminal count
CPU DMA3
CPU
DMA channel 3
terminal count
Chapter 8
CPU
329

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