upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 323

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

DMA Controller (DMAC)
8.4 Automatic Restart Function
Set DMACTn according to the following table:
The DMA source address registers (DSAHn, DSALn), DMA destination
address registers (DDAHn, DDALn), and DMA transfer count register (DBCn)
are buffer registers with a 2-stage FIFO structure, named master and slave
register.
The setup data of the slave registers is always used for the current DMA
transfer, while the master registers may hold a new setup to be used
automatically after the first DMA transfer has completed.
When the terminal count DCHCn.TCn=1 is issued, the slave registers are
automatically rewritten with the values of the master registers.
Therefore, during DMA transfer, transfer is automatically started when a new
DMA transfer setting is made for these registers and the MLEn bit of the
DCHCn register is set (however, the DMA transfer end interrupt is issued even
if DMA transfer is automatically started).
This mode is called multi link mode and is configured by DCHCn.MLEn=1.
If DMA channel n is disabled (DCHCn.ENn=0), writing to DSAH/Ln, DDAH/Ln,
DBCn stores the data to the master and slave registers.
Writing the next DMA transfer setup data to the master registers only - and to
keep the first setup data in the slave registers - is possible after
• the DMA channel n has been enabled (DCHCn.ENn=1) and
• the first DMA trigger interrupt for channel n has occurred.
The new setup data will become effective after
• the previous DMA transfer has completed (DCHC.TCn=1, INTDMAn) and
• the next following DMA trigger interrupt for channel n has occurred.
Note that the terminal count flag DCHC.TCn does not need to be cleared in
multi link mode (DCHC.MLEn = 1) for starting up the next DMA transfer
automatically.
Figure 8-1 shows the configuration of the buffer register.
Preliminary User’s Manual U17566EE1V2UM00
Source \
Destination
Internal RAM
Peripherals
Internal RAM
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1
Peripherals
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Chapter 8
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