DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 100

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–6
Figure 2–3. Address Clock Enable During Read Cycle Waveform
Figure 2–4. Address Clock Enable During the Write Cycle Waveform
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Mixed Width Support
1
latched address
(inside memory)
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
addressstall
addressstall
wraddress
q (asynch)
rdaddress
Figure 2–3
Figure 2–4
M20K memory blocks support mixed data widths inherently. MLABs can support
mixed data widths through emulation with the Quartus II software. When using
simple dual-port, true dual-port, or FIFO modes, mixed width support allows you to
read and write different data widths to a memory block. For more information about
the different widths supported per memory mode, refer to
page
MLABs do not support mixed-width FIFO mode.
q (synch)
inclock
inclock
wren
data
rden
2–8.
doutn-1
doutn
an
an
XX
shows the address clock enable waveform during the read cycle.
shows the address clock enable waveform during the write cycle.
a0
a0
00
XX
doutn
a0
a0
dout0
a1
a1
01
dout0
XX
01
02
a2
a2
XX
XX
XX
a1
dout1
a1
02
a3
a3
03
00
dout1
a4
04
a4
Chapter 2: Memory Blocks in Stratix V Devices
a4
a4
03
dout4
a5
a5
05
“Memory Modes” on
04
dout4
a5
dout5
May 2011 Altera Corporation
a5
05
a6
a6
06
Overview