DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 189

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
I/O Structure
May 2011 Altera Corporation
Open-Drain Output
Bus-Hold
Pull-Up Resistor
Pre-Emphasis
Differential Output Voltage
Stratix V devices provide an optional open-drain output (equivalent to an open
collector output) for each I/O pin. When configured as open drain, the logic value of
the output is either high-Z or 0. Typically, an external pull-up resistor is required to
provide logic high.
Each Stratix V device I/O pin provides an optional bus-hold feature. Bus-hold
circuitry can weakly hold the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, you do not require an external pull-up or pull-down resistor to hold a signal
level when the bus is tri-stated.
Bus-hold circuitry also pulls non-driven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than the
V
use the programmable pull-up option. Disable the bus-hold feature if the I/O pin is
configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (R
7 k  to weakly pull the signal level to the last-driven state.
The bus-hold circuit is active only after configuration. When going into user mode,
the bus-hold circuit captures the value on the pin that is present at the end of
configuration.
Each Stratix V device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 k  ) weakly holds the I/O to the V
Programmable pull-up resistors are only supported on user I/O pins and are not
supported on dedicated configuration pins, JTAG pins, or dedicated clock pins. If you
enable the programmable pull-up option, you cannot use the bus-hold feature.
Stratix V LVDS transmitters support programmable pre-emphasis to compensate for
the frequency dependent attenuation of the transmission line. The Quartus II software
allows two settings for programmable pre-emphasis control—0 and 1—where 0 is
disabled and 1 (default) is enabled.
Stratix V LVDS transmitters support programmable V
settings allow you to adjust output eye height to optimize trace length and power
consumption. A higher V
smaller V
settings for programmable V
medium low, 2 is medium high, and 3 is high.
CCIO
to prevent over-driving signals. If you enable the bus-hold feature, you cannot
OD
swing reduces power consumption. The Quartus II software allows four
OD
swing improves voltage margins at the receiver end; a
OD
control—0, 1, 2, and 3—where 0 is low, 1 (default) is
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CCIO
level.
OD
. The programmable V
BH
) of approximately
OD
5–13