DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 411
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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Chapter 1: Transceiver Architecture in Stratix V Devices
10G PCS Architecture
Figure 1–35. Frame Generator
Figure 1–36. CRC-32 Generator
May 2011 Altera Corporation
67
Sy SB SK
0
Total Data for CRC-32 Calculation
67
Synchronization
From TX FIFO
0
67
1
1
From the Frame Generator
Metaframe
Payload
State Word
Scrambler
The frame generator is only used in the Interlaken configuration.
CRC-32 Generator
The CRC-32 generator
The CRC-32 generator block receives data from the frame generator and calculates the
cyclic redundancy check (CRC) code for each block of data. This value is stored in the
CRC32 field of the diagnostic word.
The CRC-32 calculation covers the complete metaframe including the diagnostic
word, except the following:
■
■
■
The CRC-32 generator is only used in the Interlaken configuration.
bits [66:64] of each word
58-bit scrambler state within the scrambler state word
32-bit CRC-32 field within the diagnostic word
1-Bit Control
64-Bit Data
67
Di
Skip Word
0
Sy
SB SK
66 65 64
Generator
Frame
Data
Sync Header
Inversion Bit (Place Holder for Bit Inversion Information)
Used for Clock Compensation in a Repeater
Used to Synchronize the Scrambler
Used to Align the Lanes of the Bundle
63
(Figure
Generator
CRC-32
1–36) is designed to support the Interlaken protocol.
0
66
Payload
Sy SB SK
Total Data for CRC-32 Calculation
0
66
Stratix V Device Handbook Volume 3: Transceivers
Metaframes with Embedded
CRC-32 Code to Scrambler
66-Bit Blocks
Payload
0
Di
Calculated CRC-32 Value
Inserted in the 32 Bits
To CRC-32 Generator
66
of Diagnostic Word
Provides Per
Lane Error Check
and Optional Status
Message
31
Di
0
Sy
SB SK
1–39
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