DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 380

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–8
Stratix V Device Handbook Volume 3: Transceivers
Receiver Buffer
f
The switch from LTR to LTD mode is indicated by the assertion of the
pma_rx_is_lockedtodata signal.
In LTD mode, the CDR uses a phase detector to keep the recovered clock
phase-matched to the data. If the CDR does not stay locked to data because of
frequency drift or severe amplitude attenuation, the LTR/LTD controller switches the
CDR back to LTR mode to lock to the input reference clock. In automatic lock mode,
the LTR/LTD controller switches the CDR from LTD to LTR mode when the following
conditions are met:
■
■
The switch from LTD to LTR mode is indicated by the de-assertion of the
pma_rx_is_lockedtodata signal.
The receiver input buffers support programmable common mode voltage (RX V
equalization, DC gain, on-chip termination (OCT) settings, signal detect, and offset
cancellation. Equalization and DC gain are described in
on page
Receiver Input Buffer
The receiver input buffer receives serial data from the rx_serial_data port and feeds
it to the channel PLL configured as the CDR unit, as shown in
Figure 1–8. Receiver Input Buffer
For information about the electrical features of the receiver buffer, refer to the
Switching Characteristics for Stratix V Devices
To CDR
Detect
Signal
Signal threshold detection circuitry indicates the absence of valid signal levels at
the receiver input buffer (PCIe configuration only. This condition defaults to true
for all other configurations.)
The CDR output clock is not within the configured PPM frequency threshold
setting with respect to the input reference clock
1–9.
Receiver Input Buffer
Equalization
Threshold
Detection
DC Gain
Circuitry
Circuitry
Signal
and
Chapter 1: Transceiver Architecture in Stratix V Devices
0.82/1.1 V
chapter.
120/150 Ω
85/100 Ω
V
RX
“Receiver Analog Settings”
CM
Figure
May 2011 Altera Corporation
1–8.
From Serial Data
(rx_serial_data)
PMA Architecture
Input Pins
DC and
CM
),