DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 461

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
10GBASE-R
Figure 4–4. XGMII interface (DDR) versus Stratix V Transceiver Interface (SDR) for 10GBASE-R
May 2011 Altera Corporation
Stratix V Transceiver Interface (SDR)
Interface Clock (156.25 MHz)
Interface Clock (156.25 MHz)
XGMII Transfer (DDR)
Stratix V transceivers do not support the XGMII interface to the MAC/RS as defined
in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit
control SDR interface between the MAC/RS and the PCS, as shown in
TXD/RXD[31:0]
TXC/RXC/[3:0]
64B/66B Encoding/Decoding
Stratix V transceivers in a 10GBASE-R configuration support 64B/66B encoding and
decoding as specified in Clause 49 of the IEEE802.3-2008 specification. The 64B/66B
encoder receives 64-bit data and 8-bit control code from the transmitter FIFO and
converts it into 66-bit encoded data. The 66-bit encoded data contains two overhead
sync header bits that are used by the receiver PCS for block synchronization and
bit-error rate (BER) monitoring.
The 64B/66B encoding also ensures enough transitions on the serial data stream for
the receiver clock data recovery (CDR) to maintain its lock to the incoming data.
Transmitter and Receiver State Machines
Stratix V transceivers in a 10GBASE-R configuration implement the transmit and
receive state diagrams shown in Figure 49-14 and Figure 49-15 of the IEEE802.3-2008
specification.
Besides encoding the raw data as per the rules of the 10GBASE-R PCS, the transmit
state diagram performs functions such as transmitting local faults (LBLOCK_T) under
reset as well as transmitting error codes (EBLOCK_T) when the 10GBASE-R PCS rules
are violated.
Besides decoding the incoming data as per the rules of the 10GBASE-R PCS, the
receive state diagram performs functions such as sending local faults (LBLOCK_R) to
the MAC/RS under reset and substituting error codes (EBLOCK_R) when the
10GBASE-R PCS rules are violated.
TXD/RXD[63:0]
TXC/RXC/[7:0]
D0
C0
{D1, D0}
{C1, C0}
D1
C1
D2
C2
{D3, D2}
{C3, C2}
D3
C3
D4
C4
Stratix V Device Handbook Volume 3: Transceivers
{D5, D4}
{C5, C4}
D5
C5
D6
C6
Figure
4–4.
4–5