DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 43

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–19. Transceiver Specifications for Stratix V GX and GS Devices—Preliminary (Part 2 of 3)
May 2011 Altera Corporation
Avalon-MM PHY
management clock
frequency
Receiver
Supported I/O
Standards
Data rate
(Standard PCS)
Data rate (10G PCS)
Absolute V
receiver pin
Absolute V
receiver pin
Maximum peak-to-peak
differential input voltage
V
device configuration
Maximum peak-to-peak
differential input voltage
V
device configuration
Minimum differential
eye opening at receiver
serial input pins
Differential on-chip
termination resistors
Programmable
equalization
Programmable DC gain
ID
ID
(diff p-p) before
(diff p-p) after
Description
Symbol/
MAX
MIN
(3)
for a
for a
(4)
V
DC Gain Setting
DC Gain Setting
DC Gain Setting
DC Gain Setting
DC Gain Setting
100 setting
120 setting
150- setting
CCR_GXB
V
V
85 setting
Conditions
0.85 V and
ICM
ICM
V
CCR_GXB
and
= 0.65 V
= 0.55 V
= 0
= 1
= 2
= 3
= 4
= 1.0 V
=
2000
Min
600
-0.4
85
Speed Grade
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Commercial
Typ
100
120
150
0
2
4
6
8
–1
85
14100
8500
Max
1.2
1.6
2.2
2.6
20
Stratix V Device Handbook Volume 1: Overview and Datasheet
< 150
2000
-0.4
Commercial/Industrial
Min
600
85
Speed Grade
Typ
100
120
150
0
2
4
6
8
–2
85
12500
8500
Max
1.2
1.6
2.2
2.6
20
2000
Commercial/Industrial
Min
-0.4
600
85
(Note 1)
Speed Grade
Typ
100
120
150
0
2
4
6
8
–3
85
6500
8500
Max
1.2
1.6
2.2
2.6
20
2–15
Mbps
Mbps
MHz
Unit
mV
dB
dB
dB
dB
dB
dB
V
V
V
V
V

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