DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 446

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–30
Figure 2–23. Receiver Datapath Interface Clocking for Three Bonded Channels
Stratix V Device Handbook Volume 3: Transceivers
Data and Status Logic
Data and Status Logic
Data and Status Logic
Channel 1 Receiver
Channel 0 Receiver
Channel 2 Receiver
1
FPGA Fabric
rx_coreclkin[1]
rx_coreclkin[0]
rx_coreclkin[2]
Figure 2–23
by the tx_clkout[0] clock. The tx_clkout[0] clock is derived from the central clock
divider of channel 1 or 4 in a transceiver bank.
User-Selected Receiver Datapath Interface Clock
Multiple receiver channels that are non-bonded lead to high utilization of GCLK,
RCLK, and PCLK resources (one clock resource per channel as shown in
on page
receiver datapath clocks if the receiver channels are identical.
Identical receiver channels are defined as channels that have the same input reference
clock source for the CDR and the same receiver PMA and PCS configuration. Identical
receiver channels may have different analog settings, such as receiver common mode
voltage (V
2–29). You can significantly reduce GCLK, RCLK, and PCLK resource use for
ICM
shows the receiver datapath interface of three bonded channels clocked
), equalization, or DC gain setting.
Receiver Data
Receiver Data
Receiver Data
tx_clkout[0]
Compensation
Compensation
Compensation
Phase
Phase
Phase
FIFO
FIFO
FIFO
RX
RX
RX
Chapter 2: Transceiver Clocking in Stratix V Devices
Parallel Clock (Recovered Clock)
Parallel Clock (Recovered Clock)
Parallel Clock (Recovered Clock)
Receiver Data
Receiver Data
Receiver Data
FPGA Fabric-Transceiver Interface Clocking
May 2011 Altera Corporation
Channel 2
Channel 1
Channel 0
Figure 2–22